Usually, a sample and hold circuit is arranged in the input section of A/D converter or other converting device. It samples the input voltage at a prescribed timing, and holds the sampled voltage until the end of the conversion by the converting device. In FIG. 4(a), 102 represents a conventional sample and hold circuit.
Said sample and hold circuit 102 has a constitution comprising hold capacitor 106, analog switch 107, switch control circuit 120, and output circuit 115. When analog switch 107 is in the conductive state, sampling voltage V.sub.IN charges or discharges hold capacitor 106. On the other hand, when analog switch 107 is in the cutoff state, the charge stored in the hold capacitor 106 is maintained, and, by means of output circuit 115, the hold voltage of hold capacitor 106 is output to the next circuit stage.
This operation is performed under instruction of the sample/hold signal. The sample/hold signal is input to an inverter 121 in the switch control circuit 120.
Inverter 121 inverts the input sample/hold signal, and outputs it as the XOUT signal. This XOUT signal is output to analog switch 107 and inverter 123, said inverter 123 is inverted again, and the obtained signal is output as OUT signal to analog switch 107.
Analog switch 107 has a constitution with a p-channel MOSFET 111.sub.p and n-channel MOSFET MOSFET 111.sub.n connected in parallel. XOUT signal is input to the gate terminal of p-channel MOSFET 111.sub.p, and OUT signal is input to the gate terminal of n-channel MOSFET 111.sub.n.
Since the OUT signal is formed by inverting the XOUT signal using inverter 123, in the steady state, the logic level of XOUT signal and the logic level of OUT signal are opposite (complementary) to each other. Also, since the XOUT signal is formed by inverting the sample/hold signal using inverter 121, when the sample/hold signal is in the high level, XOUT signal is in the low level, and the OUT signal is in the high level. Consequently, when the sample/hold signal is in the high level, p-channel MOSFET 111.sub.p and n-channel MOSFET 111.sub.n are turned ON, and analog switch 107 becomes conductive. On the other hand, when the sample/hold signal is in the low level, XOUT signal goes high, while OUT signal goes low, both p-channel MOSFET 111.sub.p and n-channel MOSFET 111.sub.n are both OFF, and analog switch 107 becomes nonconductive.
In this way, as the state of the sample/hold signal is controlled to the high level (sample) and the low level (hold), p-channel MOSFET 111.sub.p and n-channel MOSFET 111.sub.n are turned ON/OFF, and analog switch 107 can be switched to the conductive state and cutoff (nonconductive) state. Consequently, it is possible to charge or discharge sample hold capacitor 106 and to maintain the voltage.
For the aforementioned XOUT signal and OUT signal, the high level refers to the level of voltage V.sub.DD on the high potential side of the power source. On the other hand, the low level refers to the level of voltage V.sub.SS on the low potential side of the power source (V.sub.DD &gt;V.sub.SS). Usually, in order to turn the MOSFET ON, it is necessary to apply a voltage higher than the threshold voltage between source and gate. In p-channel MOSFET 111.sub.p and n-channel MOSFET 111.sub.n of said analog switch 107, the source potential varies corresponding to input voltage V.sub.IN. Consequently, when the voltage between the souce and gate is lower than threshold voltages V.sub.th (p) and V.sub.th (n), it cannot become ON. The output voltage of p-channel MOSFET 111.sub.p takes on the range of symbol V.sub.p shown in FIG. 4(b), and the output voltage of n-channel MOSFET 111.sub.n takes on the range of symbol V.sub.n.
Consequently, when sample voltage V.sub.IN becomes near V.sub.DD, sampling is performed by p-channel MOSFET 111.sub.q sic; 111.sub.p ! alone; when it becomes near V.sub.SS sampling is performed by n-channel MOSFET 111.sub.n alone. In this way, by connecting p-channel MOSFET 111.sub.p and n-channel MOSFET 111.sub.n, the ranges of their output voltages Vn and Vp complement with each other to fill the range, sampling can be made in the voltage range of V.sub.SS -V.sub.DD in this constitution.
In this way, when said analog switch 107 is shifted from the conductive state to the cutoff state, as the sample/hold signal is inverted from the high level to the low level, first of all, XOUT signal makes a logic inversion from the low level (voltage V.sub.SS) to the high level (voltage V.sub.DD), p-channel MOSFET 111.sub.p is turned OFF before n-channel MOSFET 111.sub.n. In this case, the parasitic capacitance 112p formed between the gate terminal and drain terminal of p-channel MOSFET 111.sub.p is charged (discharged).
When said parasitic capacitance 112.sub.p is charged (dischargeed), as n-channel MOSFET 111.sub.n is ON, the current accompanying discharge (charging) of the parasitic capacitance flows through n-channel MOSFET 111.sub.n, and there is no change in the hold voltage.
Then, after delay by the operation time of inverter 123, logic inversion is made from the high level to the low level, and n-channel MOSFET 111.sub.n is OFF. In this case, the parasitic capacitance 112n formed between the gate terminal and source terminal of n-channel MOSFET 111.sub.n is charged (discharged). When n-channel MOSFET 111.sub.n is OFF, as p-channel MOSFET 111.sub.p is already OFF, current (i) in the case of discharging (charging) parasitic capacitance 112n flows through hold capacitor 106, and the voltage of hold capacitor 106 varies. As aforementioned, when the p-channel MOSFET is first OFF, the hold voltage level becomes lower than sampling voltage V.sub.IN, and there is an error in the hold voltage.
In this way, as the levels of power source voltages V.sub.DD and V.sub.SS vary, the error voltage also varies, and it is impossible to correct it. Consequently, efforts are made intended to solve the problem, for example, by using a hold capacitor having a capacitance larger than the parasitic capacitance. However, in this case, the chip area becomes larger than that in the case when the hold capacitor is arranged on the chip. This problem must be solved.
The purpose of this invention is to solve the aforementioned problems of the conventional methods by providing a type of waveform shaping circuit which is free of error in the sample and hold voltage, and a type of sample and hold circuit which uses the waveform shaping circuit.